chip design tools: Govt equipping over 100 colleges with cutting-edge chip design tools

The country heads of these chip design software companies told ET that training with these tools ensures that students are industry-ready when they graduate.

Globally, there are only a handful of companies that make these tools and there isn’t a single chip that can be designed without their aid.

While Siemens has been working with the IT ministry to create an EDA tools grid as a part of design-linked incentive scheme for chip startups, Synopsys has partnered with IIT Bombay, Indian Institute of Science, and Jadavpur University to develop talent for the chip industry and address workforce shortage as a part of Synopsys Academic & Research Alliances (SARA) programme.

Meanwhile, 350 engineering colleges in India have access to Cadence’s suite of EDA technologies.

Ruchir Dixit, country manager, Siemens EDA, told ET that India needs a skilled workforce that can work for the proposed chip units.

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The government’s Chips to Startups (C2S) initiative has equipped more than 100 academic institutions in the country with EDA tools from Siemens EDA and others, he said.Also read | India to soon manufacture semiconductor equipment: IT Minister Ashwini Vaishnaw

Started in January 2022, C2S aims to train 85,000 people over five years in very large-scale integration and embedded system design.

In the first round, 103 institutions and startups, including the Indian Institutes of Technology at Kanpur, Bombay, Roorkee and Dharwad, had been selected to work on projects such as global navigation receiver SoC for NAVIC and Global Positioning System (GPS), among others.

Siemens has been working with the ministry of electronics and information technology (MeitY) to create an EDA tools grid additionally as a part of design-linked incentive (DLI) scheme for startups in the semiconductor and electronics domain.

“We’ve provided our software at a donation price to colleges. This saves colleges the trouble of chasing for these tools individually, and it also allows the suite of tools to train multiple people at the same time,” Dixit said.

Raja Subramaniam, country head of Synopsys India, told ET that there’s going to be a tremendous shortage of talented manpower globally by 2030, citing a Goldman Sachs report.

Also read | Semiconductor units will strengthen India’s transformative journey for tech self-reliance: PM Modi

So, the government wants to harness the potential of Indian engineering colleges, specifically in electronics and communication engineering.

Semiconductor chip design is a complex process starting from design creation to design verification to emulation to prototyping right up till manufacturing.

“Training with these tools ensures that when the students graduate, they’re industry-ready and knowledgeable. With access to such technologies, this enables incubation of startups. Depending on the circuit being designed–digital design, analog design or mixed signal design, startups can pick up those sets of tools,” he said.

Jaswinder Ahuja, managing director, Cadence Design Systems, India, said these tools are normally very expensive. “We have made these tools available at a highly subsidised rate,” he said.

The suite that it has made available in the C2S programme has over 100 different tools.

“Students are only limited by their imagination. Designing a chip for a mobile phone is not a simple task, it takes very large teams of commercial enterprises upwards of hundreds of engineers and one or two years to design a chip of this complexity,” he explained.

In August last year, the government invited another round of applications under the C2S programme of 100 more academic institutions, research, and development (R&D) organisations, startups, micro, small and medium enterprises (MSMEs).

“However, there are many other segments of industrial control, automotive and the likes, where there are chips needed of lesser complexity. Students will be able to design chips of lesser complexity. It will give them the confidence, skills, and ability to launch a startup should they choose to do it after they graduate,” he said.

In last year’s round, MeitY had accepted proposals for work in areas of energy and environment, healthcare, agriculture, disaster management, intelligent transport, system, emerging technology, safety and security, as well as strategic projects, as per the official notification.

These tools can take thousands of engineer days to be developed. “Each one of us – Siemens EDA and other large suppliers – have thousands of engineers developing these tools and it takes years of effort to build them because they’re highly complex,” Dixit said.

As technology advances, customers want different functionality from electronic devices.

“The tooling that is required to address additional customer needs becomes extremely complex. This raises the price. What we make available to educational institutes is at a tiny fraction of a price a commercial establishment will get it at,” he said.

Dixit of Siemens EDA said, “Students can design sub-components of a chip that goes into a mobile phone, which is an extremely complex process with these tools. Subsequent batches of students can build on what their predecessors did with the tools provided. Post their graduation, a startup may emerge with the skills they were enabled with in college.”

The country heads of these chip design software companies told ET that training with these tools ensures that students are industry-ready when they graduate.

Globally, there are only a handful of companies that make these tools and there isn’t a single chip that can be designed without their aid.

While Siemens has been working with the IT ministry to create an EDA tools grid as a part of design-linked incentive scheme for chip startups, Synopsys has partnered with IIT Bombay, Indian Institute of Science, and Jadavpur University to develop talent for the chip industry and address workforce shortage as a part of Synopsys Academic & Research Alliances (SARA) programme.

Meanwhile, 350 engineering colleges in India have access to Cadence’s suite of EDA technologies.

Ruchir Dixit, country manager, Siemens EDA, told ET that India needs a skilled workforce that can work for the proposed chip units.

Discover the stories of your interest

The government’s Chips to Startups (C2S) initiative has equipped more than 100 academic institutions in the country with EDA tools from Siemens EDA and others, he said.Also read | India to soon manufacture semiconductor equipment: IT Minister Ashwini Vaishnaw

Started in January 2022, C2S aims to train 85,000 people over five years in very large-scale integration and embedded system design.

In the first round, 103 institutions and startups, including the Indian Institutes of Technology at Kanpur, Bombay, Roorkee and Dharwad, had been selected to work on projects such as global navigation receiver SoC for NAVIC and Global Positioning System (GPS), among others.

Siemens has been working with the ministry of electronics and information technology (MeitY) to create an EDA tools grid additionally as a part of design-linked incentive (DLI) scheme for startups in the semiconductor and electronics domain.

“We’ve provided our software at a donation price to colleges. This saves colleges the trouble of chasing for these tools individually, and it also allows the suite of tools to train multiple people at the same time,” Dixit said.

Raja Subramaniam, country head of Synopsys India, told ET that there’s going to be a tremendous shortage of talented manpower globally by 2030, citing a Goldman Sachs report.

Also read | Semiconductor units will strengthen India’s transformative journey for tech self-reliance: PM Modi

So, the government wants to harness the potential of Indian engineering colleges, specifically in electronics and communication engineering.

Semiconductor chip design is a complex process starting from design creation to design verification to emulation to prototyping right up till manufacturing.

“Training with these tools ensures that when the students graduate, they’re industry-ready and knowledgeable. With access to such technologies, this enables incubation of startups. Depending on the circuit being designed–digital design, analog design or mixed signal design, startups can pick up those sets of tools,” he said.

Jaswinder Ahuja, managing director, Cadence Design Systems, India, said these tools are normally very expensive. “We have made these tools available at a highly subsidised rate,” he said.

The suite that it has made available in the C2S programme has over 100 different tools.

“Students are only limited by their imagination. Designing a chip for a mobile phone is not a simple task, it takes very large teams of commercial enterprises upwards of hundreds of engineers and one or two years to design a chip of this complexity,” he explained.

In August last year, the government invited another round of applications under the C2S programme of 100 more academic institutions, research, and development (R&D) organisations, startups, micro, small and medium enterprises (MSMEs).

“However, there are many other segments of industrial control, automotive and the likes, where there are chips needed of lesser complexity. Students will be able to design chips of lesser complexity. It will give them the confidence, skills, and ability to launch a startup should they choose to do it after they graduate,” he said.

In last year’s round, MeitY had accepted proposals for work in areas of energy and environment, healthcare, agriculture, disaster management, intelligent transport, system, emerging technology, safety and security, as well as strategic projects, as per the official notification.

These tools can take thousands of engineer days to be developed. “Each one of us – Siemens EDA and other large suppliers – have thousands of engineers developing these tools and it takes years of effort to build them because they’re highly complex,” Dixit said.

As technology advances, customers want different functionality from electronic devices.

“The tooling that is required to address additional customer needs becomes extremely complex. This raises the price. What we make available to educational institutes is at a tiny fraction of a price a commercial establishment will get it at,” he said.

Dixit of Siemens EDA said, “Students can design sub-components of a chip that goes into a mobile phone, which is an extremely complex process with these tools. Subsequent batches of students can build on what their predecessors did with the tools provided. Post their graduation, a startup may emerge with the skills they were enabled with in college.”