Samsung’s new tech to make 2nm chips more powerful and efficient
According to a new report from Chosun Biz, Samsung Foundry is planning to integrate the Backside Power Delivery Network (BSPDN) technology in 2nm chips. In this technology, power lines are placed at the rear side of the wafer, which makes it easier to manufacture chips on smaller node sizes (especially node sizes smaller than 3nm) while offering reduced die size, increased power efficiency, and higher performance.
Placing power lines on the front side is becoming difficult
Currently, power lines are placed on the front side of the wafer, which is the same side where the circuit is also engraved. Placing power lines on the same side where the circuit is engraved has made it convenient to manufacture semiconductors. However, as the node size is shrinking, it is becoming difficult to place power lines on the same side where the circuit is engraved as doing so introduces interference, making the designing and manufacturing process very difficult.
BSPDN solves the issue
Implementing the BSPDN technology (placing power lines at the rear side of the wafer) helps with this exact problem as it puts power lines and circuit engraving on different sides of the wafer, reducing interference, and making the designing and manufacturing process easier. Using this technology also reduces die size and increases efficiency and performance.
Samsung Foundry has achieved excellent results
Reportedly, Samsung Foundry has tested the BSPDN technology on two ARM chips, which resulted in the reduction of the die sizes of those chips by 10% and 19% while improving performance and efficiency by a maximum of 9%. The publication also says that the test results have exceeded the company’s performance targets.
Samsung Foundry is expected to start manufacturing chips on the 2nm fabrication process in 2025. The company has also received the first order for 2nm chips and Qualcomm is also expected to knock on Samsung’s door for 2nm chips for its future SoCs.
Intel and TSMC also taking the same approach
Intel Foundry Service is also taking this approach with its 2nm chips (Intel 20A). The company calls its version of this technology Powervia. TSMC is also planning on taking this approach with its 2nm chips. Intel is expected to start manufacturing 2nm chips this year, whereas, TSMC is expected to kick off the production of 2nm chips in 2026.
According to a new report from Chosun Biz, Samsung Foundry is planning to integrate the Backside Power Delivery Network (BSPDN) technology in 2nm chips. In this technology, power lines are placed at the rear side of the wafer, which makes it easier to manufacture chips on smaller node sizes (especially node sizes smaller than 3nm) while offering reduced die size, increased power efficiency, and higher performance.
Placing power lines on the front side is becoming difficult
Currently, power lines are placed on the front side of the wafer, which is the same side where the circuit is also engraved. Placing power lines on the same side where the circuit is engraved has made it convenient to manufacture semiconductors. However, as the node size is shrinking, it is becoming difficult to place power lines on the same side where the circuit is engraved as doing so introduces interference, making the designing and manufacturing process very difficult.
BSPDN solves the issue
Implementing the BSPDN technology (placing power lines at the rear side of the wafer) helps with this exact problem as it puts power lines and circuit engraving on different sides of the wafer, reducing interference, and making the designing and manufacturing process easier. Using this technology also reduces die size and increases efficiency and performance.
Samsung Foundry has achieved excellent results
Reportedly, Samsung Foundry has tested the BSPDN technology on two ARM chips, which resulted in the reduction of the die sizes of those chips by 10% and 19% while improving performance and efficiency by a maximum of 9%. The publication also says that the test results have exceeded the company’s performance targets.
Samsung Foundry is expected to start manufacturing chips on the 2nm fabrication process in 2025. The company has also received the first order for 2nm chips and Qualcomm is also expected to knock on Samsung’s door for 2nm chips for its future SoCs.
Intel and TSMC also taking the same approach
Intel Foundry Service is also taking this approach with its 2nm chips (Intel 20A). The company calls its version of this technology Powervia. TSMC is also planning on taking this approach with its 2nm chips. Intel is expected to start manufacturing 2nm chips this year, whereas, TSMC is expected to kick off the production of 2nm chips in 2026.
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